Embodiments of the invention relate generally to phase locked loop (PLL) circuits and in particular to PLL circuits with voltage controlled oscillator (VCO) circuits having controllable (or maintainable) biasing.
PLL circuits are used to control the frequency and/or phase of a clock signal. They typically have a voltage controlled oscillator (VCO) circuit for controlling a signal's frequency based on the value of an input signal such as an input voltage. The performance of a PLL may depend on the performance capability of the VCO and its immunity to distortion such as thermal noise. Accordingly, improved PLL designs less sensitive to noise are desired.